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CDP1854A/3, CDP1854AC/3
High Reliability CMOS Programmable Universal Asynchronous Receiver/Transmitter (UART)
Description
The CDP1854A/3 and CDP1854AC/3 are high reliability silicon gate CMOS Universal Asynchronous Receiver/Transmitter (UART) circuits. They are designed to provide the necessary formatting and control for interfacing between serial and parallel data. For example, these UARTs can be used to interface between a peripheral or terminal with serial I/O ports and the 8-bit CDP1800-series microprocessor parallel data bus system. The CDP1854A/3 is capable of full duplex operation, i.e., simultaneous conversion of serial input data to parallel output data and parallel input data to serial output data. The CDP1854A/3 UART can be programmed to operate in one of two modes by using the mode control input. When the mode input is high (MODE = 1), the CDP1854A/3 is directly compatible with the CDP1800 series microprocessor system without additional interface circuitry. When the mode input is low (MODE = 0), the device is functionally compatible with industry standard UARTs such as the TR1602A and CDP6402. It is also pin compatible with these types, except that pin 2 is used for the mode control input. The CDP1854A/3 and the CDP1854AC/3 are functionally identical. The CDP1854A/3 has a recommended operating voltage range of 4V to 10.5V, and the CDP1854AC/3 has a recommended operating voltage range of 4V to 6.5V.
March 1997
Features
* Two Operating Modes - Mode 0 - Functionally Compatible with Industry Types Such as the TR1602A and CDP6402 - Mode 1 - Interfaces Directly with CDP1800 Series Microprocessors without Additional Components * Full or Half-Duplex Operation * Parity, Framing, and Overrun Error Detection * Fully Programmable with Externally Selectable Word Length (5-8 Bits), Parity Inhibit, Even/Odd Parity, and 1, 1-1/2, or 2 Stop Bits
Ordering Information
PACKAGE
SBDIP
TEMP. RANGE
5V/200K BAUD
10V/400K BAUD
PKG. NO.
-55oC to +125oC CDP1854ACD3 CDP1854ACD3 D40.6
Pinouts
CDP1854A/3, CDP1854AC/3 (SBDIP) (MODE 0) TOP VIEW
VDD 1 MODE (VSS) 2 VSS 3 RRD 4 R BUS 7 5 R BUS 6 6 R BUS 5 7 R BUS 4 8 R BUS 3 9 R BUS 2 10 R BUS 1 11 R BUS 0 12 PE 13 FE 14 OE 15 SFD 16 R CLOCK 17 DAR 18 DA 19 SDI 20
40 T CLOCK 39 EPE 38 WLS 1 37 WLS 2 36 SBS 35 PI 34 CRL 33 T BUS 7 32 T BUS 6 31 T BUS 5 30 T BUS 4 29 T BUS 3 28 T BUS 2 27 T BUS 1 26 T BUS 0 25 SD0 24 TSRE 23 THRL 22 THRE 21 MR
CDP1854A/3, CDP1854AC/3 (SBDIP) (MODE 1) TOP VIEW
VDD 1 MODE (VDD) 2 VSS 3 CS2 4 R BUS 7 5 R BUS 6 6 R BUS 5 7 R BUS 4 8 R BUS 3 9 R BUS 2 10 R BUS 1 11 R BUS 0 12 INT 13 FE 14 PE/OE 15 RSEL 16 R CLOCK 17 TPB 18 DA 19 SDI 20
NC = NO CONNECT 40 T CLOCK 39 CTS 38 ES 37 PS1 36 NC 35 CS3 34 RD/WR 33 T BUS 7 32 T BUS 6 31 T BUS 5 30 T BUS 4 29 T BUS 3 28 T BUS 2 27 T BUS 1 26 T BUS 0 25 SD0 24 RTS 23 CS1 22 THRE 21 CLEAR
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved 1
File Number
1715.2
CDP1854A/3, CDP1854AC/3
Absolute Maximum Ratings
DC Supply-Voltage Range, (VDD) (All voltages referenced to VSS terminal) CDP1854A/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +11V CDP1854AC/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . . -0.5 to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . . 10mA Device Dissipation Per Output Transistor For TA = Full Package-Temperature Range . . . . . . . . . . . 100mW Operating-Temperature Range (TA) Package Type D . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) SBDIP Package. . . . . . . . . . . . . . . . . . 55 15 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150oC Maximum Storage Temperature Range (TSTG) . . .-65oC to +150oC Maximum Lead Temperature (Soldering 10s) At Distance 1/16 1/32 inch (1.59 0.79mm) . . . . . . . . . . +265oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Static Electrical Specifications
CONDITIONS -55oC, +25oC PARAMETER Quiescent Device Current IDD VO (V) Output Low Drive (Sink) Current Output High Drive (Source) Current Output Voltage Low-Level (Note 1) Output Voltage High Level (Note 1) Input Low Voltage IOL 0.4 0.5 IOH 4.6 9.5 VOL VOH VIL 0.5, 4.5 0.5, 9.5 Input High Voltage VIH 0.5, 4.5 0.5, 9.5 Input Leakage Current IIN Three-State Output Leakage Current Input Capacitance (Note 1) Output Capacitance (Note 1) NOTE: 1. Guaranteed but not tested. IOUT 0, 5 0, 10 CIN COUT VIN (V) 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 VDD (V) 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 MIN 0.75 1.80 4.9 9.9 3.5 7 MAX 500 500 -0.5 -1.0 0.1 0.1 1.5 3 1 1 1 1 10 15 LIMITS +125oC MIN 0.5 1.2 4.9 9.8 3.5 7 MAX 1000 1000 -0.35 -0.70 0.2 0.2 1.5 3 5 5 10 10 10 15 UNITS A A mA mA mA mA V V V V V V V V A A A A pF pF
2
Specifications CDP1854A/3, CDP1854AC/3
Operating Conditions
At TA = Full Package-Temperature Range. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: CONDITIONS -55oC, +25oC PARAMETER DC Operating Voltage Range Input Voltage Range Baud Rate (Receive or Transmit) VDD (V) 5 10 MIN 4 VSS MAX 10.5 VDD 250 520 MIN 4 VSS LIMITS +125oC MAX 6.5 VDD 215 430 UNITS V V K bits/s K bits/s
Dynamic Electrical Specifications
t R, t F = 15ns, VIH = VDD , VIL = VSS , CL = 100pF, (See Figure 1) LIMITS -55oC, +25oC +125oC MIN MAX UNITS
PARAMETER TRANSMITTER TIMING - MODE 1 Clock Period tCC
VDD (V)
MIN
MAX
5 10
240 120
-
280 145
-
ns ns
Pulse Width Clock Low Level
tCL 5 10 105 55 135 65 125 70 125 65 155 80 165 80 ns ns ns ns ns ns
Clock High Level
tCH
5 10
TPB
tTT
5 10
Propagation Delay Time Clock to Data Start Bit
tCD 5 10 425 205 315 155 335 160 485 235 380 185 390 190 ns ns ns ns ns ns
TPB to THRE
tTTH
5 10
Clock to THRE
tCTH
5 10
3
CDP1854A/3, CDP1854AC/3
Dynamic Electrical Specifications
t R, t F = 15ns, VIH = VDD , VIL = VSS , CL = 100pF, (See Figure 2) LIMITS -55oC, +25oC PARAMETER RECEIVER TIMING - MODE 1 Clock Period tCC 5 10 Pulse Width Clock Low Level tCL 5 10 Clock High Level tCH 5 10 TPB tTT 5 10 Setup Time Data Start Bit to Clock tDC 5 10 Propagation Delay Time TPB to DATA AVAILABLE tTDA 5 10 Clock to DATA AVAILABLE tCDA 5 10 Clock to Overrun Error tCOE 5 10 Clock to Parity Error tCPE 5 10 Clock to Framing Error tCFE 5 10 295 150 305 150 305 150 305 150 280 145 340 170 355 170 330 175 330 175 330 165 ns ns ns ns ns ns ns ns ns ns 105 65 120 70 ns ns 105 55 135 65 125 70 125 65 155 80 165 80 ns ns ns ns ns ns 240 120 280 145 ns ns VDD (V) MIN MAX MIN +125oC MAX UNITS
4
CDP1854A/3, CDP1854AC/3
TRANSMITTER HOLDING REGISTER LOADED (NOTE 1) TRANSMITTER SHIFT REGISTER LOADED (NOTE 2) tCC tCH T CLOCK 1 2 3 tCL 4 5 6 7 14 15 16 1 2 tCD WRITE (TPB) (NOTE 3) tTT THRE tTTH tCD SDO 1ST DATA BIT tCTH 3 4
NOTES: 1. The holding register is loaded on the trailing edge of TPB. 2. The transmitter shift register, if empty, is loaded on the first high-to-low transition of the clock which occurs at least 1/2 clock period + tTC after the trailing edge of TPB and transmission of a start bit occurs 1/2 clock period + tCD later. 3. Write is the overlap of TPB, CS1, and CS3 = 1 and CS3, RD/WR = 0 FIGURE 1. TRANSMITTER TIMING DIAGRAM - MODE 1
tCC tCH R CLOCK tDC (NOTE 1) SDI tCL 1 2 3 4
CLOCK 7 1/2 SAMPLE 5 6 7 16 1 2
CLOCK 7 1/2 LOAD HOLDING REGISTER 3 4 5 6 7 8 9
START BIT tTDA
PARITY
STOP BIT 1 tCDA
DA
READ (NOTE 2) tTT TPB tCOE OE (NOTE 3) PE (NOTE 3)
tCPE
tCFE
FE
NOTES: 1. If a start bit occurs at a time less than tDC before a high-to-low transition of the clock, the start bit may not be recognized until the next high-to-low transition of the clock. The start bit may be completely asynchronous with the clock. 2. Read is the overlap of CS1, CS3, RD/WR = 1 and CS2 = 0. If a pending DA has not been cleared by a read of the receiver holding register by the time a new word is loaded into the receiver holding register, the OE signal will come true. 3. OE and PE share terminal 15 and are also available as two separate bits in the status register. FIGURE 2. MODE 1 RECEIVER TIMING DIAGRAM
5
CDP1854A/3, CDP1854AC/3
Dynamic Electrical Specifications
t R, t F = 15ns, VIH = VDD , VIL = VSS , CL = 100pF, (See Figure 3) LIMITS -55oC, +25oC PARAMETER CPU INTERFACE - WRITE TIMING - MODE 1 Pulse Width TPB tTT 5 10 Setup Time RSEL to Write tRSW 5 10 Data to Write tDW 5 10 Hold Time RSEL after Write tWRS 5 10 Data after Write tWD 5 10 -10 5 95 55 -20 5 105 55 ns ns ns ns 20 25 65 45 10 25 75 50 ns ns ns ns 125 70 165 80 ns ns VDD (V) MIN MAX MIN +125oC MAX UNITS
tTT TPB (NOTE 1) tRSW RSEL tDW T BUS 0T BUS 7 tWD tWRS
CS3, CS1 (NOTE 1)
RD/WR, CS2 (NOTE 1)
NOTE: 1. Write is the overlap of TPB, CS1, CS3 = 1 and CS2, RD/WR = 0. FIGURE 3. MODE 1 CPU INTERFACE (WRITE) TIMING DIAGRAM
6
CDP1854A/3, CDP1854AC/3
Dynamic Electrical Specifications
t R, t F = 15ns, VIH = VDD , VIL = VSS , CL = 100pF, (See Figure 4) LIMITS -55oC, +25oC PARAMETER CPU INTERFACE - READ TIMING - MODE 1 Pulse Width TPB tTT 5 10 Setup Time RSEL to TPB tRST 5 10 Hold Time RSEL after TPB tTRS 5 10 Propagation Delay Time Read to Data Valid Time tRDV 5 10 RESEL to Data Valid Time tRSDV 5 10 360 165 250 125 420 195 295 145 ns ns ns ns -10 5 -25 0 ns ns 15 20 0 10 ns ns 125 70 165 80 ns ns VDD (V) MIN MAX MIN +125oC MAX UNITS
tTT TPB tRST RSEL tRSDV R BUS 0R BUS 7 tRDV RD/WR, CS1, CS3 (NOTE 1) tTRS
CS2
NOTE: 1. Read is the overlap of CS1, CS3, RD/WR = 1 and CS2 = 0. FIGURE 4. MODE 1 CPU INTERFACE (READ) TIMING DIAGRAM
7
CDP1854A/3, CDP1854AC/3
Dynamic Electrical Specifications
t R, t F = 15ns, VIH = VDD , VIL = VSS , CL = 100pF, (See Figure 5) LIMITS VDD (V) -55oC, +25oC MIN MAX MIN +125oC MAX UNITS
PARAMETER INTERFACE TIMING - MODE 0 Pulse Width CRL tCRL
5 10
105 55 340 160
-
125 65 385 175
-
ns ns ns ns
MR
tMR
5 10
Setup Time Control Word to CRL tCWC 5 10 Hold Time Control Word after CRL tCCW 5 10 Propagation Delay Time SFD High to SOD tSFDH 5 10 SFD Low to SOD tSFDL 5 10 RRD High to Receiver Register High Impedance RRD Low to Receiver Register Active tRRDH 5 10 tRRDL 5 10 165 90 165 90 175 105 185 110 195 105 195 105 195 115 205 130 ns ns ns ns ns ns ns ns 65 45 65 45 ns ns 80 40 85 60 ns ns
CONTROL INPUT WORD TIMING CONTROL WORD INPUT CONTROL WORD BYTE tCWC CRL tCRL STATUS OUTPUT TIMING STATUS OUTPUTS tSFDH SFD tSFDL tCCW
RECEIVER REGISTER DISCONNECT TIMING R BUS 0 R BUS 7 tRRDH RRD tRRDL
FIGURE 5. MODE 0 INTERFACE TIMING DIAGRAM
8
CDP1854A/3, CDP1854AC/3
Dynamic Electrical Specifications
t R, t F = 15ns, VIH = VDD , VIL = VSS , CL = 100pF, (See Figure 6) LIMITS VDD (V) -55oC, +25oC MIN MAX MIN +125oC MAX UNITS
PARAMETER TRANSMITTER TIMING - MODE 0 Clock Period tCC
5 10
240 120
-
280 145
-
ns ns
Pulse Width Clock Low Level tCL 5 10 Clock High Level tCH 5 10 THRL tTHTH 5 10 Setup Time THRL to Clock tTHC 5 10 Data to THRL tDT 5 10 Hold Time Data after THRL tTD 5 10 Propagation Delay Time Clock to Data Start Bit tCD 5 10 Clock to THRE tCT 5 10 THRL to THRE tTTHR 5 10 Clock to TSRE tTTS 5 10 435 205 345 175 275 145 345 165 505 235 420 200 325 165 405 190 ns ns ns ns ns ns ns ns 60 45 95 75 ns ns 205 120 25 20 235 140 30 25 ns ns ns ns 105 55 135 65 140 80 125 65 155 80 165 85 ns ns ns ns ns ns
9
CDP1854A/3, CDP1854AC/3
TRANSMITTER HOLDING REGISTER LOADED (NOTE 1) tCC tCH T CLOCK tTHC THRL tTHTH SDO tTTHR THRE tTTS TSRE T BUS 0 T BUS 7 tDT DATA tTD tCT tCD tCD 1ST DATA BIT tCL 1 TRANSMITTER SHIFT REGISTER LOADED (NOTE 2) 2 3 4 5 6 7 14 15 16 1 2 3
NOTES: 1. The holding register is loaded on the trailing edge of THRL. 2. The transmitter shift register, if empty, is loaded on the first high-to-low transition of the clock which occurs at least 1/2 clock period + tTHC after the trailing edge of THRL and transmission of a start bit occurs 1/2 clock period + tCD later. FIGURE 6. MODE 0 TRANSMITTER TIMING DIAGRAM
tCC tCH R CLOCK tDC (NOTE 1) SDI R BUS 0 R BUS 7 tCL 1 2 3 4
CLOCK 7 1/2 SAMPLE 5 6 7 16 1 2
CLOCK 7 1/2 LOAD HOLDING REGISTER 3 4 5 6 7 8 9
START BIT
PARITY
STOP BIT 1 tCDV DATA
DA tDDA DAR tDD OE (NOTE 2) PE tCFE FE tCOE tCDA
tCPE
NOTES: 1. If a start bit occurs at a time less than tDC before a high-to-low transition of the clock, the start bit may not be recognized until the next high-to-low transition of the clock. The start bit may be completely asynchronous with the clock. 2. If a pending DA has not been cleared by a read of the receiver holding register by the time a new word is loaded into the receiver holding register, the OE signal will come true. FIGURE 7. MODE 0 RECEIVER TIMING DIAGRAM
10
CDP1854A/3, CDP1854AC/3
Dynamic Electrical Specifications
t R, t F = 15ns, VIH = VDD , VIL = VSS , CL = 100pF, (See Figure 7) LIMITS VDD (V) -55oC, +25oC MIN MAX MIN +125oC MAX UNITS
PARAMETER RECEIVER TIMING - MODE 0 Clock Period tCC
5 10
240 120
-
280 145
-
ns ns
Pulse Width Clock Low Level tCL 5 10 Clock High Level tCH 5 10 DATA AVAILABLE RESET tDD 5 10 Setup Time Data Start Bit to Clock tDC 5 10 Propagation Delay Time DATA AVAILABLE RESET to Data Available Clock to Data Valid tDDA 5 10 tCDV 5 10 Clock to Data Available tCDA 5 10 Clock to Overrun Error tCOE 5 10 Clock to Parity Error tCPE 5 10 Clock to Framing Error tCFE 5 10 240 130 360 175 320 155 365 170 275 135 270 135 280 145 420 195 375 180 415 190 320 155 320 165 ns ns ns ns ns ns ns ns ns ns ns ns 105 65 130 85 ns ns 105 55 135 65 75 45 125 65 155 80 90 50 ns ns ns ns ns ns
11
CDP1854A/3, CDP1854AC/3
16 / fCLOCK NEXT DATA WORD 5 - 8 DATA BITS START BIT DATA LSB DATA MSB PARITY BIT STOP BITS 1, 1-1/2 OR 2
FIGURE 8. SERIAL DATA WORD FORMAT
Burn-In Circuit
VDD VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VDD VSS
ALL RESISTORS ARE 47k 20%
TYPE CDP1854A/3 CDP1854AC/3
VDD 11 7
TEMPERATURE +125oC +125oC
TIME 160 hrs. 160 hrs.
FIGURE 9. BIAS/STATIC BURN-IN CIRCUIT
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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